Classic Timing Analyzer report for citac
Thu Apr 15 13:04:59 2010
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tco
  7. tpd
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                       ;
+------------------------------+-------+---------------+----------------------------------+------+-------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From ; To    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+------+-------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 31.500 ns                        ; 41   ; AQ2   ; CLK        ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 20.900 ns                        ; CLR  ; LED_a ; --         ; --       ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 105.26 MHz ( period = 9.500 ns ) ; 15   ; 17    ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;      ;       ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+------+-------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EPF10K70RC240-4    ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                             ;
+-------+------------------------------------------------+------+----+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+----+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 105.26 MHz ( period = 9.500 ns )               ; 15   ; 17 ; CLK        ; CLK      ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 117.65 MHz ( period = 8.500 ns )               ; 42   ; 17 ; CLK        ; CLK      ; None                        ; None                      ; 4.500 ns                ;
; N/A   ; 117.65 MHz ( period = 8.500 ns )               ; 42   ; 15 ; CLK        ; CLK      ; None                        ; None                      ; 4.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 17   ; 17 ; CLK        ; CLK      ; None                        ; None                      ; 2.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 41   ; 41 ; CLK        ; CLK      ; None                        ; None                      ; 2.200 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 44   ; 44 ; CLK        ; CLK      ; None                        ; None                      ; 2.200 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 42   ; 42 ; CLK        ; CLK      ; None                        ; None                      ; 2.200 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 15   ; 15 ; CLK        ; CLK      ; None                        ; None                      ; 2.200 ns                ;
+-------+------------------------------------------------+------+----+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+------+-------+------------+
; Slack ; Required tco ; Actual tco ; From ; To    ; From Clock ;
+-------+--------------+------------+------+-------+------------+
; N/A   ; None         ; 31.500 ns  ; 41   ; AQ2   ; CLK        ;
; N/A   ; None         ; 27.000 ns  ; 44   ; AQ1   ; CLK        ;
; N/A   ; None         ; 23.500 ns  ; 15   ; LED_b ; CLK        ;
; N/A   ; None         ; 23.100 ns  ; 15   ; LED_c ; CLK        ;
; N/A   ; None         ; 23.100 ns  ; 15   ; LED_a ; CLK        ;
; N/A   ; None         ; 22.800 ns  ; 42   ; LED_b ; CLK        ;
; N/A   ; None         ; 22.700 ns  ; 42   ; LED_c ; CLK        ;
; N/A   ; None         ; 22.200 ns  ; 42   ; LED_a ; CLK        ;
; N/A   ; None         ; 22.200 ns  ; 17   ; LED_a ; CLK        ;
; N/A   ; None         ; 22.100 ns  ; 15   ; LED_e ; CLK        ;
; N/A   ; None         ; 21.800 ns  ; 15   ; LED_f ; CLK        ;
; N/A   ; None         ; 21.500 ns  ; 15   ; LED_g ; CLK        ;
; N/A   ; None         ; 21.500 ns  ; 15   ; LED_d ; CLK        ;
; N/A   ; None         ; 21.400 ns  ; 42   ; LED_f ; CLK        ;
; N/A   ; None         ; 21.100 ns  ; 42   ; LED_e ; CLK        ;
; N/A   ; None         ; 20.500 ns  ; 42   ; LED_g ; CLK        ;
; N/A   ; None         ; 20.500 ns  ; 42   ; LED_d ; CLK        ;
; N/A   ; None         ; 20.400 ns  ; 17   ; LED_c ; CLK        ;
; N/A   ; None         ; 20.200 ns  ; 17   ; LED_b ; CLK        ;
; N/A   ; None         ; 19.100 ns  ; 17   ; LED_f ; CLK        ;
; N/A   ; None         ; 19.100 ns  ; 17   ; LED_e ; CLK        ;
; N/A   ; None         ; 18.500 ns  ; 17   ; LED_g ; CLK        ;
; N/A   ; None         ; 18.500 ns  ; 17   ; LED_d ; CLK        ;
; N/A   ; None         ; 14.600 ns  ; 42   ; AQ0   ; CLK        ;
+-------+--------------+------------+------+-------+------------+


+------------------------------------------------------------+
; tpd                                                        ;
+-------+-------------------+-----------------+------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To    ;
+-------+-------------------+-----------------+------+-------+
; N/A   ; None              ; 20.900 ns       ; CLR  ; LED_b ;
; N/A   ; None              ; 20.900 ns       ; CLR  ; LED_a ;
; N/A   ; None              ; 20.800 ns       ; CLR  ; LED_c ;
; N/A   ; None              ; 19.500 ns       ; CLR  ; LED_f ;
; N/A   ; None              ; 19.500 ns       ; CLR  ; LED_e ;
; N/A   ; None              ; 18.900 ns       ; CLR  ; LED_g ;
; N/A   ; None              ; 18.900 ns       ; CLR  ; LED_d ;
+-------+-------------------+-----------------+------+-------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Thu Apr 15 13:04:57 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off citac -c citac
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "42" as buffer
    Info: Detected ripple clock "44" as buffer
Info: Clock "CLK" has Internal fmax of 105.26 MHz between source register "15" and destination register "17" (period= 9.5 ns)
    Info: + Longest register to register delay is 5.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H28; Fanout = 9; REG Node = '15'
        Info: 2: + IC(3.500 ns) + CELL(2.000 ns) = 5.500 ns; Loc. = LC1_H47; Fanout = 8; REG Node = '17'
        Info: Total cell delay = 2.000 ns ( 36.36 % )
        Info: Total interconnect delay = 3.500 ns ( 63.64 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 7.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'CLK'
            Info: 2: + IC(4.100 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC1_H47; Fanout = 8; REG Node = '17'
            Info: Total cell delay = 2.900 ns ( 41.43 % )
            Info: Total interconnect delay = 4.100 ns ( 58.57 % )
        Info: - Longest clock path from clock "CLK" to source register is 7.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'CLK'
            Info: 2: + IC(4.100 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC1_H28; Fanout = 9; REG Node = '15'
            Info: Total cell delay = 2.900 ns ( 41.43 % )
            Info: Total interconnect delay = 4.100 ns ( 58.57 % )
    Info: + Micro clock to output delay of source is 1.400 ns
    Info: + Micro setup delay of destination is 2.600 ns
Info: tco from clock "CLK" to destination pin "AQ2" through register "41" is 31.500 ns
    Info: + Longest clock path from clock "CLK" to source register is 22.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 12; REG Node = '42'
        Info: 3: + IC(9.700 ns) + CELL(1.400 ns) = 19.500 ns; Loc. = LC4_I7; Fanout = 3; REG Node = '44'
        Info: 4: + IC(3.100 ns) + CELL(0.000 ns) = 22.600 ns; Loc. = LC2_I22; Fanout = 2; REG Node = '41'
        Info: Total cell delay = 5.700 ns ( 25.22 % )
        Info: Total interconnect delay = 16.900 ns ( 74.78 % )
    Info: + Micro clock to output delay of source is 1.400 ns
    Info: + Longest register to pin delay is 7.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_I22; Fanout = 2; REG Node = '41'
        Info: 2: + IC(2.500 ns) + CELL(5.000 ns) = 7.500 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'AQ2'
        Info: Total cell delay = 5.000 ns ( 66.67 % )
        Info: Total interconnect delay = 2.500 ns ( 33.33 % )
Info: Longest tpd from source pin "CLR" to destination pin "LED_b" is 20.900 ns
    Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_212; Fanout = 12; PIN Node = 'CLR'
    Info: 2: + IC(6.400 ns) + CELL(2.700 ns) = 12.000 ns; Loc. = LC4_H47; Fanout = 1; COMB Node = '7447:inst|82~56'
    Info: 3: + IC(3.900 ns) + CELL(5.000 ns) = 20.900 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'LED_b'
    Info: Total cell delay = 10.600 ns ( 50.72 % )
    Info: Total interconnect delay = 10.300 ns ( 49.28 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 133 megabytes
    Info: Processing ended: Thu Apr 15 13:04:59 2010
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01


