-- aritmeticko-logická jednotka

package ALU_TYPY is
  type OPTYPE is (add, sub, mul, div);
end ALU_TYPY;

use work.ALU_TYPY.all;
entity ALU is
  port (A, B : in integer;
        OPER : in OPTYPE;
        Y : out integer);
end alu;

architecture ALU_BODY of ALU is
begin

  ALU_P: process (A, B, OPER)
  begin
    case OPER is
      when add => Y <= A + B;
      when sub => Y <= A - B;
      when mul => Y <= A * B;
      when div => Y <= A / B;
      when others => null;
    end case;
  end process;

end ALU_BODY;
-- dekoder BCD na sedmisegmentový displej

library ieee;
use ieee.std_logic_1164.all;

entity bcd_seg is 
port (
  bcdInputs: in std_logic_vector (3 downto 0);
  segment  : out std_logic_vector (6 downto 0));
end bcd_seg;

architecture a_bcd of bcd_seg is
begin
  process (bcdInputs) 
  begin

    case bcdInputs is
      when "0000" => segment <= "0000001";     
      when "0001" => segment <= "1001111";
      when "0010" => segment <= "0010010";
      when "0011" => segment <= "0000110";
      when "0100" => segment <= "1001100";
      when "0101" => segment <= "0100100";
      when "0110" => segment <= "0100000";
      when "0111" => segment <= "0001111";
      when "1000" => segment <= "0000000";
      when "1001" => segment <= "0000100";
      when others => segment <= "ZZZZZZZ";
    end case;

  end process;
end a_bcd;
-- Dvou kanalovy demultiplexor pomoci prirazeni s konstrukci when-else

entity dmx1_2 is
   port (
      x 	: in  bit;
      a 	: in  bit;
      y0, y1 	: out bit
   );
end dmx1_2;

architecture dmx of dmx1_2 is
begin
   y0 <= x when a = '0' else '0';
   y1 <= x when a = '1' else '0';
end dmx;
-- enkoder pomocí prikazu if

entity encoder_if is
  port (
	invec	: in  bit_vector(3 downto 0);
        enc_out	: out bit_vector(1 downto 0)
        );
end encoder_if;

architecture a_enc of encoder_if is
begin

	process (invec)	
	begin

		if 	  invec(3) = '1' then enc_out <= "11"; 
		elsif invec(2) = '1' then enc_out <= "10"; 
		elsif invec(1) = '1' then enc_out <= "01"; 
		else enc_out <= "00";  
		end if;

	end process;
end a_enc;
-- enkoder

entity encoder is
  port (
	invec	: in  bit_vector(3 downto 0);
        enc_out	: out bit_vector(1 downto 0)
        );
end encoder;

architecture rtl of encoder is

begin
  enc_out <= "11" when invec(3) = '1' else
             "10" when invec(2) = '1' else
             "01" when invec(1) = '1' else
             "00" when invec(0) = '1' else
             "00";

end rtl;
-- invertor

entity INVERTOR is port (
    i: in bit;
    o: out bit
    );
end INVERTOR;

architecture rtl of INVERTOR is

begin

  o <= not i;

end rtl;
-- kombinacni logicky obvod

entity klo_if is
port (A,B,C,X 	: in integer range 0 to 7;
	  Z 	: out integer range 0 to 7);
end klo_if;

architecture a_if of klo_if is
begin
  process (A,B,C,X)
  begin

	if (X > 5) then
		Z <= A ;
	elsif (X < 5) then
		Z <= B ;
	else
		Z <= C ;
	end if ;

  end process ;
end a_if ;

-- kombinacni logicky obvod

entity klo is
port (
	A,B,C,X : in  integer range 0 to 7;
	  Z 	: out integer range 0 to 7
);
end klo;

architecture a_podm of klo is
begin
   Z <= A when X > 5 else
	B when X < 5 else
    	C ;
end a_podm ;
entity MUX_CASE is
  port (
	B 	: in bit_vector (3 downto 0);
        SEL 	: in bit_vector (1 downto 0);
        Y 	: out bit
	);
end MUX_CASE;


architecture MUX_BODY of MUX_CASE is
begin
  process (B, SEL)
  begin

    case SEL is
      when "00" => Y <= B(0);
      when "01" => Y <= B(1);
      when "10" => Y <= B(2);
      when "11" => Y <= B(3);
    end case;

  end process;
end MUX_BODY;
-- Dvou kanalovy multiplexor pomoci konstrukce when-else

entity mux2_1 is
   port (
      x0, x1 	: in  bit;
      a 	: in  bit;
      y 	: out bit
   );
end mux2_1;

architecture mux of mux2_1 is
begin
   y <= x1 when a = '1' else x0;
end mux;
--multiplexer 4 na 1

ENTITY mux4_1 IS
	PORT
	(	d0, d1, d2, d3	: IN  BIT;
		s		: IN  INTEGER RANGE 0 TO 3;	
		output		: OUT BIT	);
END mux4_1;

ARCHITECTURE amux OF mux4_1 IS
BEGIN

WITH s SELECT
	output <=	d0 WHEN 0,
			d1 WHEN 1,
			d2 WHEN 2,
			d3 WHEN 3;
		
END amux;

-- nasobicka

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY nasobeni IS
	PORT (
		operand: 		IN unsigned (1 DOWNTO 0);
		soucin: 		OUT unsigned (4 DOWNTO 0)
	) ;
END nasobeni;

ARCHITECTURE rtl OF nasobeni IS
CONSTANT dvojka : unsigned (2 DOWNTO 0) := "101";

BEGIN
	soucin <= dvojka * operand;		
END rtl;
-- scitacka s prenosem

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity overflow is 
   port (
        a,b: in std_logic_vector(3 downto 0);
        sum: out std_logic_vector(3 downto 0);
        overflow: out std_logic 
        );
end overflow;

architecture a of overflow is
signal localSum: std_logic_vector(4 downto 0);

begin

  localSum <= ('0' & a) + ('0' & b);
  sum <= localSum(3 downto 0);
  overflow <= localSum(4);

end a;