-- dvoumístny dekadicky citac s dekodérem

ENTITY celek IS
	PORT(
	   clk			: IN	bit;
	   segment1, segment2 	: OUT bit_vector(7 downto 0));
END celek;

ARCHITECTURE ar_celek OF celek IS
COMPONENT citac IS
	PORT(
	   clk			: IN	bit;
	   citac1, citac2 	: BUFFER integer range 0 to 9);
END COMPONENT;

COMPONENT dekoder IS
	PORT(vstup : IN integer range 0 to 9;
	   segment : OUT bit_vector(7 downto 0));
END COMPONENT;

SIGNAL citac1 : integer range 0 to 9;
SIGNAL citac2 : integer range 0 to 9;

BEGIN
COMP1 : citac     PORT MAP (clk => clk, citac1 => citac1, citac2 => citac2);
COMP2 : dekoder	  PORT MAP (vstup => citac1, segment => segment1);
COMP3 : dekoder   PORT MAP (vstup => citac2, segment => segment2);

END ar_celek;

-- ruzne druhy citacu

ENTITY counters IS

	PORT
	(
	d			: IN 	INTEGER RANGE 0 TO 255;
	clk			: IN	BIT;
	clear			: IN	BIT;
	ld			: IN	BIT;
	enable			: IN	BIT;
	up_down			: IN	BIT;
	qa,qb,qc,qd,qe,qf,qg 	: OUT 	INTEGER RANGE 0 TO 255;
	qh,qi,qj,qk,ql,qm,qn 	: OUT 	INTEGER RANGE 0 TO 255;
	);
	
END counters;

ARCHITECTURE a_count OF counters IS
BEGIN
	-- An enable counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF enable = '1' THEN
				cnt := cnt + 1;
			END IF;
		END IF;
		
		qa	<= cnt;

	END PROCESS;

	-- A synchronous load counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF ld = '0' THEN
				cnt := d;
			ELSE
				cnt := cnt + 1;
			END IF;
		END IF;

		qb	<=	cnt;
	END PROCESS;

	-- A synchronous clear counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF clear = '0' THEN
				cnt := 0;
			ELSE
				cnt := cnt + 1;
			END IF;
		END IF;

		qc	<=	cnt;
	
	END PROCESS;

	-- An up/down counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
		VARIABLE	direction 	: INTEGER;
	BEGIN
		IF (up_down = '1') THEN
			direction := 1;
		ELSE
			direction := -1;
		END IF;
		
		IF (clk'EVENT AND clk = '1') THEN
			cnt := cnt + direction;
		END IF;

		qd	<=	cnt;
	
	END PROCESS;

	-- A synchronous load enable counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF ld = '0' THEN
				cnt := d;
			ELSE
				IF enable = '1' THEN
					cnt := cnt + 1;
				END IF;
			END IF;
		END IF;

		qe	<=	cnt;
	
	END PROCESS;

	-- An enable up/down counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
		VARIABLE	direction 	: INTEGER;
	BEGIN
		IF (up_down = '1') THEN
			direction := 1;
		ELSE
			direction := -1;
		END IF;
		
		IF (clk'EVENT AND clk = '1') THEN
			IF enable = '1' THEN
				cnt := cnt + direction;
			END IF;
		END IF;

		qf	<=	cnt;
	
	END PROCESS;

	-- A synchronous clear enable counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF clear = '0' THEN
				cnt := 0;
			ELSE
				IF enable = '1' THEN
					cnt := cnt + 1;
				END IF;
			END IF;
		END IF;

		qg	<=	cnt;
	
	END PROCESS;

	-- A synchronous load clear counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF clear = '0' THEN
				cnt := 0;
			ELSE
				IF ld = '0' THEN
					cnt := d;
				ELSE
					cnt := cnt + 1;
				END IF;
			END IF;
		END IF;

		qh	<=	cnt;
	
	END PROCESS;

	-- A synchronous load up/down counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
		VARIABLE	direction 	: INTEGER;
	BEGIN
		IF (up_down = '1') THEN
			direction := 1;
		ELSE
			direction := -1;
		END IF;
		
		IF (clk'EVENT AND clk = '1') THEN
			IF ld = '0' THEN
				cnt := d;
			ELSE
				cnt := cnt + direction;
			END IF;
		END IF;

		qi	<=	cnt;
	
	END PROCESS;

	-- A synchronous load enable up/down counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
		VARIABLE	direction 	: INTEGER;
	BEGIN
		IF (up_down = '1') THEN
			direction := 1;
		ELSE
			direction := -1;
		END IF;
		
		IF (clk'EVENT AND clk = '1') THEN
			IF ld = '0' THEN
				cnt := d;
			ELSE
				IF enable = '1' THEN
					cnt := cnt + direction;
				END IF;
			END IF;
		END IF;

		qj	<=	cnt;

	END PROCESS;

	-- A synchronous clear load enable counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF clear = '0' THEN
				cnt := 0;
			ELSE
				IF ld = '0' THEN
					cnt := d;
				ELSE
					IF enable = '1' THEN
						cnt := cnt + 1;
					END IF;
				END IF;
			END IF;
		END IF;
		
		qk	<=	cnt;
	
	END PROCESS;

	-- A synchronous clear up/down counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
		VARIABLE	direction 	: INTEGER;
	BEGIN
		IF (up_down = '1') THEN
			direction := 1;
		ELSE
			direction := -1;
		END IF;
		
		IF (clk'EVENT AND clk = '1') THEN
			IF clear = '0' THEN
				cnt := 0;
			ELSE
				cnt := cnt + direction;
			END IF;
		END IF;

		ql	<=	cnt;
	
	END PROCESS;

	-- A synchronous clear enable up/down counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
		VARIABLE	direction 	: INTEGER;
	BEGIN
		IF (up_down = '1') THEN
			direction := 1;
		ELSE
			direction := -1;
		END IF;
		
		IF (clk'EVENT AND clk = '1') THEN
			IF clear = '0' THEN
				cnt := 0;
			ELSE
				IF enable = '1' THEN
					cnt := cnt + direction;
				END IF;
			END IF;
		END IF;

		qm	<=	cnt;
	
	END PROCESS;

	-- A modulus 200 up counter
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 255;
		CONSTANT	modulus 	: INTEGER := 200;
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF cnt = modulus THEN
				cnt := 0;
			ELSE
				cnt := cnt + 1;
			END IF;
		END IF;

		qn	<=	cnt;
	
	END PROCESS;
END a_count;

-- dvoumístny dekadicky citac

ENTITY dek_cit_2 IS
	PORT(
	   clk			: IN	bit;
	   segment1, segment2 	: OUT bit_vector(0 to 7)
	);
END dek_cit_2;

ARCHITECTURE ar OF dek_cit_2 IS
	SIGNAL citac1 : integer range 0 to 9;
	SIGNAL citac2 : integer range 0 to 9;
BEGIN
		
	PROCESS (clk)
	BEGIN
		IF (clk'event and clk = '1') THEN
			citac1 <= citac1 + 1 ;
			IF (citac1 >= 9) THEN
				citac1 <= 0;
				citac2 <= citac2 + 1;
				IF (citac2 >= 9) THEN
					citac2 <= 0;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (citac1) 
	BEGIN
		CASE citac1 IS
			WHEN 0 => segment1 <= "00000011";     
			WHEN 1 => segment1 <= "10011111";
			WHEN 2 => segment1 <= "00100101";
			WHEN 3 => segment1 <= "00001101";
			WHEN 4 => segment1 <= "10011001";
			WHEN 5 => segment1 <= "01001001";
			WHEN 6 => segment1 <= "01000001";
			WHEN 7 => segment1 <= "00011111";
			WHEN 8 => segment1 <= "00000001";
			WHEN 9 => segment1 <= "00001001";
			WHEN others => segment1 <= "11111101";
		END CASE;
	END PROCESS;

	PROCESS (citac2) 
	BEGIN
		CASE citac2 IS
			WHEN 0 => segment2 <= "00000011";     
			WHEN 1 => segment2 <= "10011111";
			WHEN 2 => segment2 <= "00100101";
			WHEN 3 => segment2 <= "00001101";
			WHEN 4 => segment2 <= "10011001";
			WHEN 5 => segment2 <= "01001001";
			WHEN 6 => segment2 <= "01000001";
			WHEN 7 => segment2 <= "00011111";
			WHEN 8 => segment2 <= "00000001";
			WHEN 9 => segment2 <= "00001001";
			WHEN others => segment2 <= "11111101";
	    END CASE;
  END PROCESS;

END ar;

-- KO typu D (vcetne signalu enable) 

library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is port (
    d: in std_logic;
    clk: in std_logic;
    en: in std_logic;
    q: out std_logic
    );
end DFF;

architecture rtl of DFF is

begin

  process (clk) begin
    if clk'event and clk = '1' then
      if en = '1' then
        q <= d;
      end if;
    end if;
  end process;

end rtl;
-- KO typu D (vcetne signalu enable)

library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is port (
    d: in std_logic;
    clk: in std_logic;
    en: in std_logic;
    q: out std_logic
    );
end DFF;

architecture rtl of DFF is

begin

  process begin
    wait until rising_edge(clk);
      if en = '1' then
        q <= d;
      end if;
  end process;

end rtl;
-- KO typu JK s resetem

library ieee;
use ieee.std_logic_1164.all;

entity JK_FF is
port (	clock:		in std_logic;
	J, K:		in std_logic;
	reset:		in std_logic;
	Q, Qbar:	out std_logic);
end JK_FF;

architecture behv of JK_FF is
    signal state: std_logic;
    signal input: std_logic_vector(1 downto 0);

begin
    input <= J & K;		

    p: process(clock, reset) is
    begin
	
	if (reset='1') then
	    state <= '0';
	elsif (rising_edge(clock)) then
	    case (input) is
			when "11" =>    state <= not state;
			when "10" =>    state <= '1';
			when "01" =>    state <= '0';
			when others =>  state <= state;
		end case;
	end if;

    end process;
	
    Q <= state;
    Qbar <= not state;

end behv;
--  Klopny obvod typu latch realizovany pomoci procesu

library ieee;
use ieee.std_logic_1164.all;

entity latch_pr is
   port (
      d : in std_logic;
      en : in std_logic;
      q : out std_logic
   );
end latch_pr;

architecture struct of latch_pr is
begin
   process (d, en)
   begin
      if en = '1' then
         q <= d;
      end if;
   end process;
end struct;
-- Citac modulo 10

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity modulo10 is
   port (
      reset : in std_logic;
      clk : in std_logic;
      q : out std_logic_vector (3 downto 0)
   );
end modulo10;

architecture struct of modulo10 is
begin
   process (reset, clk)
      variable cnt : unsigned (3 downto 0);
   begin
      if reset = '1' then
         cnt := (others => '0');
      elsif clk'event and clk = '1' then
         if cnt = 9 then
            cnt := (others => '0');
         else
            cnt := cnt + 1;
         end if;
      end if;
      q <= std_logic_vector (cnt);
   end process;
end struct;
-- Parametrizovatelny dvojsmerny posuvny registr

library ieee;
use ieee.std_logic_1164.all;

entity posuv_reg_bi is
   generic (
      n : positive := 8
   );
   port (
      clk : in std_logic;
      dir : in std_logic;
      sdl : in std_logic;
      sdr : in std_logic;
      q : out std_logic_vector (1 to n)
   );
end posuv_reg_bi;

architecture struct of posuv_reg_bi is
   signal reg : std_logic_vector (1 to n);
begin
   process (clk)
   begin
      if clk'event and clk = '1' then
         if dir = '1' then
            reg <= sdl & reg (1 to n - 1);
         else
            reg <= reg (2 to n) & sdr;
         end if;
      end if;
   end process;
   q <= reg;
end struct;
-- 12-bitovy registr

ENTITY reg12 IS
	PORT(
		d		: IN   BIT_VECTOR(11 DOWNTO 0);
		clk		: IN   BIT;
		q		: OUT  BIT_VECTOR(11 DOWNTO 0));
END reg12;

ARCHITECTURE a OF reg12 IS
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL clk = '1';
		q <= d;
	END PROCESS;
END a;

-- realizace 24-bitovégo registru ze dvou 12-bitovych
-- soubor reg12.vhd musí být součástí (přidán do) projektu

ENTITY reg24a IS
	PORT(
		d		: IN   BIT_VECTOR(23 DOWNTO 0);
		clk		: IN   BIT;
		q		: OUT  BIT_VECTOR(23 DOWNTO 0));
END reg24a;

ARCHITECTURE a OF reg24a IS
BEGIN
	reg12a	: ENTITY work.reg12 PORT MAP (d => d(11 DOWNTO 0), clk => clk, 
			  q => q(11 DOWNTO  0));
	reg12b	: ENTITY work.reg12 PORT MAP (d => d(23 DOWNTO 12), clk => clk, 
			  q => q(23 DOWNTO 12));
END a;

-- realizace 24-bitovégo registru ze dvou 12-bitovych

PACKAGE reg24_package IS
	COMPONENT reg12
		PORT(
			d	: IN	BIT_VECTOR(11 DOWNTO 0);
			clk	: IN	BIT;
			q	: OUT	BIT_VECTOR(11 DOWNTO 0));
	END COMPONENT;
END reg24_package;

LIBRARY work;
USE work.reg24_package.ALL;

ENTITY reg24 IS
	PORT(
		d		: IN   BIT_VECTOR(23 DOWNTO 0);
		clk		: IN   BIT;
		q		: OUT  BIT_VECTOR(23 DOWNTO 0));
END reg24;

ARCHITECTURE a OF reg24 IS
BEGIN
	reg12a	: reg12 PORT MAP (d => d(11 DOWNTO 0), clk => clk, 
			  q => q(11 DOWNTO  0));
	reg12b	: reg12 PORT MAP (d => d(23 DOWNTO 12), clk => clk, 
			  q => q(23 DOWNTO 12));
END a;

-- 16-bitovy posuvny registr

library IEEE;
use IEEE.std_logic_1164.all;

entity shifter is port (
  clk, rst: in std_logic;
  shiftEn,shiftIn: std_logic;
  q: out std_logic_vector (15 downto 0)
  );
end shifter;


architecture behav of shifter is

signal qLocal: std_logic_vector(15 downto 0);

begin

  shift: process (clk, rst) begin
    if (rst = '1') then
      qLocal <= (others => '0');
    elsif (clk'event and clk = '1') then
      if (shiftEn = '1') then
        qLocal <= qLocal(14 downto 0) & shiftIn;
      else
        qLocal <= qLocal;
      end if;
    end if;

    q <= qLocal;
  end process;

end behav;
-- popis hradla XOR

ENTITY  x_or  IS
	PORT ( in1, in2 : IN BIT;
               out1 : OUT BIT );
END x_or;

ENTITY  hr_and  IS
	PORT ( a, b : IN BIT;
	          c : OUT BIT );
END hr_and;

ARCHITECTURE  behavior  OF  hr_and  IS
BEGIN
	PROCESS (a, b)
		BEGIN 
		    c <=  a AND b AFTER 5 ns;
	END PROCESS;
END behavior;

ENTITY  hr_or  IS
	PORT ( d, e : IN BIT;
	          f : OUT BIT );
END hr_or;

ARCHITECTURE  behavior OF hr_or IS
BEGIN
	PROCESS (d, e)
		BEGIN 
		    f <=  d OR e AFTER 4 ns;
	END PROCESS;
END behavior;

ENTITY  invert  IS
	PORT ( g : IN BIT;
           h : OUT BIT );
END invert;
ARCHITECTURE  behavior OF invert IS
BEGIN
	PROCESS (g)
		BEGIN 
		    h <=  NOT  g  AFTER 3 ns;
	END PROCESS;
END behavior;

ARCHITECTURE  structural OF x_or IS
SIGNAL t1, t2, t3, t4 : BIT;

COMPONENT hr_and
	PORT( a, b	: IN	BIT;
		  c	: OUT	BIT);
END COMPONENT;

COMPONENT  hr_or
	PORT (d, e : IN BIT;
	         f : OUT BIT );
END COMPONENT;

COMPONENT  invert
	PORT (	g : IN BIT;
		h : OUT BIT );
END COMPONENT;

BEGIN
	u0: hr_and PORT MAP (a=>t1, b=>in2, c=>t3);
	u1: hr_and PORT MAP (a=>in1, b=>t2, c=>t4);
	u2: invert PORT MAP (g=>in1, h=>t1);
	u3: invert PORT MAP (g=>in2, h=>t2);
	u4: hr_or PORT MAP (d=>t3, e=>t4, f=>out1);
END structural;