library IEEE;
use IEEE.std_logic_1164.all;

entity bit_tribuf is
    port (
	Din : in bit;
	Enable: in bit;
	Dout : out STD_LOGIC
	);
end bit_tribuf;

architecture bit_tribuf_arch of bit_tribuf is
    
begin
    Dout <= To_StdULogic(Din) when Enable='1' else
            'Z';
end bit_tribuf_arch;

library IEEE;
use IEEE.std_logic_1164.all;

package decProcs is

  procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
                    decode: out std_logic_vector(3 downto 0)
                   );
end decProcs;

package body decProcs is

  procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
                    decode: out std_logic_vector(3 downto 0)
                   ) is
  begin
    case inputs is
      when "11" =>
        decode := "1000";
      when "10" =>
        decode := "0100";
      when "01" =>
        decode := "0010";
      when "00" =>
        decode := "0001";
      when others =>
        decode := "0001";
    end case;
  end DEC2x4;

end decProcs;
library IEEE;
use IEEE.std_logic_1164.all;

use work.decProcs.all;

entity decoder is port (
  decIn: in std_logic_vector(1 downto 0);
  decOut: out std_logic_vector(3 downto 0)
  );
end decoder;

architecture simple of decoder is

begin

  DEC2x4(decIn,decOut);

end simple;

library IEEE;
use IEEE.std_logic_1164.all;

entity decoder is port (
  decIn: in std_logic_vector(1 downto 0);
  decOut: out std_logic_vector(3 downto 0)
  );
end decoder;

architecture simple of decoder is

  procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
                    decode: out std_logic_vector(3 downto 0)
                   ) is
  begin
    case inputs is
      when "11" =>
        decode := "1000";
      when "10" =>
        decode := "0100";
      when "01" =>
        decode := "0010";
      when "00" =>
        decode := "0001";
      when others =>
        decode := "0001";
    end case;
  end DEC2x4;

begin

  DEC2x4(decIn,decOut);

end simple;

PACKAGE pkg_fce IS
  	CONSTANT max : INTEGER := 150 ;
	FUNCTION check_max(a: INTEGER) RETURN BIT;
END pkg_fce;

PACKAGE BODY pkg_fce IS
	FUNCTION check_max(a: INTEGER) RETURN BIT IS
   		VARIABLE t: BIT;
	BEGIN
    	IF (a > MAX) THEN t:= '1';
	    ELSE              t:= '0';
    	END IF;
		RETURN(t);
	END check_max;
END pkg_fce;
library ieee;
use ieee.std_logic_1164.all;

entity mealy is
	port (clock, reset : in std_logic;
	   data_out : out std_logic;
	   data_in : in std_logic_vector (1 downto 0));
end mealy;

architecture behave of mealy is
	type hodnoty_stavu is (ST0, ST1, ST2, ST3, ST4);
	signal akt_stav, nasl_stav : hodnoty_stavu;
begin
reg: process (clock, reset) 		-- registrova cast
begin
	if (reset = '0') then 
		akt_stav <= ST0;
	elsif (clock'event and clock = '1') then
		akt_stav <= nasl_stav;
	end if;
end process reg;

komb: process (akt_stav, data_in) 	-- kombinacni cast
begin
	case akt_stav is
		when ST0 => 
			case data_in is
				when "00" 	=> nasl_stav <= ST0;
				when "01" 	=> nasl_stav <= ST4;
				when "10" 	=> nasl_stav <= ST1;
				when "11" 	=> nasl_stav <= ST2;
				when others => nasl_stav <= ST0;
			end case;
		when ST1 => 
			case data_in is
				when "00" 	=> nasl_stav <= ST0;
				when "10" 	=> nasl_stav <= ST2;
				when others => nasl_stav <= ST1;
			end case;
		when ST2 => 
			case data_in is
				when "00" 	=> nasl_stav <= ST1;
				when "01" 	=> nasl_stav <= ST1;
				when "10" 	=> nasl_stav <= ST3;
				when "11" 	=> nasl_stav <= ST3;
				when others => nasl_stav <= ST0;
			end case;
		when ST3 => 
			case data_in is
				when "01" 	=> nasl_stav <= ST4;
				when "11" 	=> nasl_stav <= ST4;
				when others => nasl_stav <= ST3;
			end case;
		when ST4 => 
			case data_in is
				when "11" 	=> nasl_stav <= ST4;
				when others => nasl_stav <= ST0;
			end case;
		when others => nasl_stav <= ST0;
	end case;
end process komb;

vyst: process (akt_stav, data_in)	-- vystupni funkce
begin
	case akt_stav is
		when ST0 =>
			case data_in is
				when "00" 	=> data_out <= '0';
				when others => data_out <= '1';
			end case;
		when ST1 => data_out <= '0';
		when ST2 =>
			case data_in is
				when "00" 	=> data_out <= '0';
				when "01" 	=> data_out <= '0';
				when others => data_out <= '1';
			end case;
		when ST3 => data_out <= '1';
		when ST4 =>
			case data_in is
				when "10" 	=> data_out <= '1';
				when "11" 	=> data_out <= '1';
				when others => data_out <= '0';
			end case;
		when others => data_out <= '0';
	end case;
end process vyst;

end behave;
-- Konecny automat typu Moore

library ieee;
use ieee.std_logic_1164.all;

entity moore is
   port (
      clk : in std_logic;
      i0, i1, i2 : in std_logic;
      o0, o1, o2 : out std_logic
   );
end moore;

architecture behav of moore is
   type stavy is (s0, s1, s2, s3);
   signal stav_reg, dalsi_stav : stavy := s0;
begin
   -- realizace pameti stavu automatu
   process (clk)
   begin
      if clk'event and clk = '1' then
         stav_reg <= dalsi_stav;
      end if;
   end process;

   -- prechodova funkce automatu
   process (stav_reg, i0, i1, i2)
   begin
      case stav_reg is
         when s0 =>
            if i0 = '1' or i2 = '1' then
               dalsi_stav <= s1;
            end if;
         when s1 =>
            if i0 = '1' then
               dalsi_stav <= s2;
            elsif i1 = '1' then
               dalsi_stav <= s0;
            elsif i2 = '1' then
               dalsi_stav <= s3;
            end if;
         when s2 =>
            if i1 = '1' then
               dalsi_stav <= s0;
            end if;
         when s3 =>
             dalsi_stav <= s3;
         when others =>
            dalsi_stav <= stav_reg;
      end case;
   end process;

   -- vystupni funkce automatu
   process (stav_reg)
   begin
      case stav_reg is
         when s0 =>
            o0 <= '1';
            o1 <= '0';
            o2 <= '0';
         when s1 =>
            o0 <= '1';
            o1 <= '0';
            o2 <= '0';
         when s2 =>
            o0 <= '0';
            o1 <= '1';
            o2 <= '0';
         when s3 =>
            o0 <= '0';
            o1 <= '0';
            o2 <= '1';
         when others => null;
      end case;
   end process;
end behav;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux_3s IS
PORT (a,b,c,d: 	IN  std_logic_vector(3 DOWNTO 0);
    	    s:	IN  std_logic_vector(1 DOWNTO 0);
           oe:	IN  std_logic;
         x_3s: 	OUT std_logic_vector(3 DOWNTO 0));
END mux_3s;

ARCHITECTURE amux_3s OF mux_3s IS
SIGNAL pom: std_logic_vector(3 DOWNTO 0);
BEGIN

WITH s SELECT
	pom <= 	a WHEN "00",
		b WHEN "01",
		c WHEN "10",
		d WHEN OTHERS;

PROCESS (oe,pom)
	BEGIN
	    IF oe = '0' THEN x_3s <= (OTHERS => 'Z');
	    ELSE x_3s <= pom;
	    END IF;
	END PROCESS;

END amux_3s;

-- druhy proces lze nahradit podminecnym prirazenim:
-- x_3s <= pom WHEN oe = '1' ELSE 'Z';LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY regbidir IS
PORT ( q: INOUT	std_logic_vector(7 DOWNTO 0);
      en: IN 	std_logic;
      oe: IN 	std_logic);
END regbidir;

ARCHITECTURE areg OF regbidir IS
SIGNAL qa: std_logic_vector(7 DOWNTO 0);
BEGIN

PROCESS (en,q)
BEGIN
	IF en = '1'	THEN qa <= q;
	END IF;
END PROCESS;

PROCESS (oe,qa)
BEGIN
	IF oe = '0' THEN q <= (OTHERS => 'Z');
	ELSE q <= qa;
        END IF;
END PROCESS;

END areg;
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity tribuf8 is
  port (
    Din    : in  bit_vector(7 downto 0);
    Enable : in  bit;
    Dout   : out STD_LOGIC_VECTOR(7 downto 0));
end tribuf8;

architecture tribuf8_arch of tribuf8 is
component bit_tribuf 
    port (
	Din : in bit;
	Enable: in bit;
	Dout : out STD_LOGIC
	);
end component;

begin 
all_buf: for i in 7 downto 0 generate
    one_buf: bit_tribuf port map (
      Din    => Din(i),
      Enable => Enable,
      Dout   => Dout(i));
  end generate all_buf;
end tribuf8_arch;