TimeQuest Timing Analyzer report for druhy
Thu Apr 29 17:46:20 2010
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Clocks
  4. Slow 1200mV 85C Model Fmax Summary
  5. Slow 1200mV 85C Model Setup Summary
  6. Slow 1200mV 85C Model Hold Summary
  7. Slow 1200mV 85C Model Recovery Summary
  8. Slow 1200mV 85C Model Removal Summary
  9. Slow 1200mV 85C Model Minimum Pulse Width
 10. Clock to Output Times
 11. Minimum Clock to Output Times
 12. Slow 1200mV 0C Model Fmax Summary
 13. Slow 1200mV 0C Model Setup Summary
 14. Slow 1200mV 0C Model Hold Summary
 15. Slow 1200mV 0C Model Recovery Summary
 16. Slow 1200mV 0C Model Removal Summary
 17. Slow 1200mV 0C Model Minimum Pulse Width
 18. Clock to Output Times
 19. Minimum Clock to Output Times
 20. Fast 1200mV 0C Model Setup Summary
 21. Fast 1200mV 0C Model Hold Summary
 22. Fast 1200mV 0C Model Recovery Summary
 23. Fast 1200mV 0C Model Removal Summary
 24. Fast 1200mV 0C Model Minimum Pulse Width
 25. Clock to Output Times
 26. Minimum Clock to Output Times
 27. Multicorner Timing Analysis Summary
 28. Clock to Output Times
 29. Minimum Clock to Output Times
 30. Board Trace Model Assignments
 31. Input Transition Times
 32. Slow Corner Signal Integrity Metrics
 33. Fast Corner Signal Integrity Metrics
 34. Setup Transfers
 35. Hold Transfers
 36. Report TCCS
 37. Report RSKM
 38. Unconstrained Paths
 39. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                    ;
+--------------------+-------------------------------------------------+
; Quartus II Version ; Version 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name      ; druhy                                           ;
; Device Family      ; Cyclone III                                     ;
; Device Name        ; EP3C5E144C8                                     ;
; Timing Models      ; Final                                           ;
; Delay Model        ; Combined                                        ;
; Rise/Fall Delays   ; Enabled                                         ;
+--------------------+-------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                          ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; clk        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+


+----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                       ;
+-----------+-----------------+------------+---------------------------------------------------------------+
; Fmax      ; Restricted Fmax ; Clock Name ; Note                                                          ;
+-----------+-----------------+------------+---------------------------------------------------------------+
; 485.2 MHz ; 250.0 MHz       ; clk        ; limit due to minimum period restriction (max I/O toggle rate) ;
+-----------+-----------------+------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+-------+--------+--------------------+
; Clock ; Slack  ; End Point TNS      ;
+-------+--------+--------------------+
; clk   ; -1.061 ; -3.011             ;
+-------+--------+--------------------+


+------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+-------+-------+--------------------+
; Clock ; Slack ; End Point TNS      ;
+-------+-------+--------------------+
; clk   ; 0.464 ; 0.000              ;
+-------+-------+--------------------+


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+-------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width                                                       ;
+--------+--------------+----------------+-------+------------------+-------+------------+--------+
; Slack  ; Actual Width ; Required Width ; CCPP  ; Type             ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-------+------------------+-------+------------+--------+
; -3.000 ; 1.000        ; 4.000          ; 0.000 ; Port Rate        ; clk   ; Rise       ; clk    ;
; -1.857 ; 1.000        ; 2.857          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[0] ;
; -1.857 ; 1.000        ; 2.857          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[1] ;
; -1.857 ; 1.000        ; 2.857          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[2] ;
; -1.857 ; 1.000        ; 2.857          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[3] ;
; 0.238  ; 0.330        ; 0.188          ; 0.096 ; Low Pulse Width  ; clk   ; Rise       ; cnt[0] ;
; 0.238  ; 0.330        ; 0.188          ; 0.096 ; Low Pulse Width  ; clk   ; Rise       ; cnt[1] ;
; 0.238  ; 0.330        ; 0.188          ; 0.096 ; Low Pulse Width  ; clk   ; Rise       ; cnt[2] ;
; 0.238  ; 0.330        ; 0.188          ; 0.096 ; Low Pulse Width  ; clk   ; Rise       ; cnt[3] ;
; 0.353  ; 0.477        ; 0.220          ; 0.096 ; High Pulse Width ; clk   ; Rise       ; cnt[0] ;
; 0.353  ; 0.477        ; 0.220          ; 0.096 ; High Pulse Width ; clk   ; Rise       ; cnt[1] ;
; 0.353  ; 0.477        ; 0.220          ; 0.096 ; High Pulse Width ; clk   ; Rise       ; cnt[2] ;
; 0.353  ; 0.477        ; 0.220          ; 0.096 ; High Pulse Width ; clk   ; Rise       ; cnt[3] ;
+--------+--------------+----------------+-------+------------------+-------+------------+--------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 7.758 ; 7.726 ; Rise       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 6.936 ; 6.870 ; Rise       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                         ;
+------------+-----------------+------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
+------------+-----------------+------------+---------------------------------------------------------------+
; 534.47 MHz ; 250.0 MHz       ; clk        ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+-------+--------+-------------------+
; Clock ; Slack  ; End Point TNS     ;
+-------+--------+-------------------+
; clk   ; -0.871 ; -2.441            ;
+-------+--------+-------------------+


+-----------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+-------+-------+-------------------+
; Clock ; Slack ; End Point TNS     ;
+-------+-------+-------------------+
; clk   ; 0.415 ; 0.000             ;
+-------+-------+-------------------+


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+-------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width                                                        ;
+--------+--------------+----------------+-------+------------------+-------+------------+--------+
; Slack  ; Actual Width ; Required Width ; CCPP  ; Type             ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-------+------------------+-------+------------+--------+
; -3.000 ; 1.000        ; 4.000          ; 0.000 ; Port Rate        ; clk   ; Rise       ; clk    ;
; -1.857 ; 1.000        ; 2.857          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[0] ;
; -1.857 ; 1.000        ; 2.857          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[1] ;
; -1.857 ; 1.000        ; 2.857          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[2] ;
; -1.857 ; 1.000        ; 2.857          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[3] ;
; 0.237  ; 0.336        ; 0.184          ; 0.085 ; Low Pulse Width  ; clk   ; Rise       ; cnt[0] ;
; 0.237  ; 0.336        ; 0.184          ; 0.085 ; Low Pulse Width  ; clk   ; Rise       ; cnt[1] ;
; 0.237  ; 0.336        ; 0.184          ; 0.085 ; Low Pulse Width  ; clk   ; Rise       ; cnt[2] ;
; 0.237  ; 0.336        ; 0.184          ; 0.085 ; Low Pulse Width  ; clk   ; Rise       ; cnt[3] ;
; 0.361  ; 0.492        ; 0.216          ; 0.085 ; High Pulse Width ; clk   ; Rise       ; cnt[0] ;
; 0.361  ; 0.492        ; 0.216          ; 0.085 ; High Pulse Width ; clk   ; Rise       ; cnt[1] ;
; 0.361  ; 0.492        ; 0.216          ; 0.085 ; High Pulse Width ; clk   ; Rise       ; cnt[2] ;
; 0.361  ; 0.492        ; 0.216          ; 0.085 ; High Pulse Width ; clk   ; Rise       ; cnt[3] ;
+--------+--------------+----------------+-------+------------------+-------+------------+--------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 7.397 ; 7.337 ; Rise       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 6.607 ; 6.515 ; Rise       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+-------+-------+--------------------+
; Clock ; Slack ; End Point TNS      ;
+-------+-------+--------------------+
; clk   ; 0.127 ; 0.000              ;
+-------+-------+--------------------+


+-----------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+-------+-------+-------------------+
; Clock ; Slack ; End Point TNS     ;
+-------+-------+-------------------+
; clk   ; 0.193 ; 0.000             ;
+-------+-------+-------------------+


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+-------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width                                                        ;
+--------+--------------+----------------+-------+------------------+-------+------------+--------+
; Slack  ; Actual Width ; Required Width ; CCPP  ; Type             ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-------+------------------+-------+------------+--------+
; -3.000 ; 1.000        ; 4.000          ; 0.000 ; Port Rate        ; clk   ; Rise       ; clk    ;
; -1.000 ; 1.000        ; 2.000          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[0] ;
; -1.000 ; 1.000        ; 2.000          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[1] ;
; -1.000 ; 1.000        ; 2.000          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[2] ;
; -1.000 ; 1.000        ; 2.000          ; 0.000 ; Min Period       ; clk   ; Rise       ; cnt[3] ;
; -0.237 ; -0.098       ; 0.184          ; 0.045 ; Low Pulse Width  ; clk   ; Rise       ; cnt[0] ;
; -0.237 ; -0.098       ; 0.184          ; 0.045 ; Low Pulse Width  ; clk   ; Rise       ; cnt[1] ;
; -0.237 ; -0.098       ; 0.184          ; 0.045 ; Low Pulse Width  ; clk   ; Rise       ; cnt[2] ;
; -0.237 ; -0.098       ; 0.184          ; 0.045 ; Low Pulse Width  ; clk   ; Rise       ; cnt[3] ;
; 0.834  ; 1.005        ; 0.216          ; 0.045 ; High Pulse Width ; clk   ; Rise       ; cnt[0] ;
; 0.834  ; 1.005        ; 0.216          ; 0.045 ; High Pulse Width ; clk   ; Rise       ; cnt[1] ;
; 0.834  ; 1.005        ; 0.216          ; 0.045 ; High Pulse Width ; clk   ; Rise       ; cnt[2] ;
; 0.834  ; 1.005        ; 0.216          ; 0.045 ; High Pulse Width ; clk   ; Rise       ; cnt[3] ;
+--------+--------------+----------------+-------+------------------+-------+------------+--------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 3.550 ; 3.603 ; Rise       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 3.195 ; 3.236 ; Rise       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                          ;
+------------------+--------+-------+----------+---------+---------------------+
; Clock            ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack ; -1.061 ; 0.0   ; 0.0      ; 0.0     ; -3.000              ;
;  clk             ; -1.061 ; 0.193 ; N/A      ; N/A     ; N/A                 ;
; Design-wide TNS  ; -3.011 ; 0.0   ; 0.0      ; 0.0     ; N/A                 ;
;  clk             ; -3.011 ; 0.000 ; N/A      ; N/A     ; N/A                 ;
+------------------+--------+-------+----------+---------+---------------------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 7.758 ; 7.726 ; Rise       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 3.195 ; 3.236 ; Rise       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; q             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; clk                     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; q             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-007 V                  ; 2.34 V              ; -0.00824 V          ; 0.14 V                               ; 0.017 V                              ; 6.89e-010 s                 ; 6.56e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-007 V                 ; 2.34 V             ; -0.00824 V         ; 0.14 V                              ; 0.017 V                             ; 6.89e-010 s                ; 6.56e-010 s                ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.53e-007 V                  ; 2.35 V              ; -0.00333 V          ; 0.096 V                              ; 0.006 V                              ; 4.5e-010 s                  ; 3.85e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.53e-007 V                 ; 2.35 V             ; -0.00333 V         ; 0.096 V                             ; 0.006 V                             ; 4.5e-010 s                 ; 3.85e-010 s                ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.51e-007 V                  ; 2.34 V              ; -0.00718 V          ; 0.108 V                              ; 0.027 V                              ; 6.58e-010 s                 ; 8.2e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.51e-007 V                 ; 2.34 V             ; -0.00718 V         ; 0.108 V                             ; 0.027 V                             ; 6.58e-010 s                ; 8.2e-010 s                 ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; q             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.72e-008 V                  ; 2.71 V              ; -0.0349 V           ; 0.145 V                              ; 0.063 V                              ; 4.5e-010 s                  ; 4.15e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.72e-008 V                 ; 2.71 V             ; -0.0349 V          ; 0.145 V                             ; 0.063 V                             ; 4.5e-010 s                 ; 4.15e-010 s                ; No                        ; Yes                       ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.17e-008 V                  ; 2.74 V              ; -0.061 V            ; 0.159 V                              ; 0.078 V                              ; 2.7e-010 s                  ; 2.2e-010 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.17e-008 V                 ; 2.74 V             ; -0.061 V           ; 0.159 V                             ; 0.078 V                             ; 2.7e-010 s                 ; 2.2e-010 s                 ; No                        ; Yes                       ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.54e-008 V                  ; 2.7 V               ; -0.0113 V           ; 0.274 V                              ; 0.034 V                              ; 3.18e-010 s                 ; 4.96e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.54e-008 V                 ; 2.7 V              ; -0.0113 V          ; 0.274 V                             ; 0.034 V                             ; 3.18e-010 s                ; 4.96e-010 s                ; No                        ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------+
; Setup Transfers                                                   ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk        ; clk      ; 10       ; 0        ; 0        ; 0        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------+
; Hold Transfers                                                    ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk        ; clk      ; 10       ; 0        ; 0        ; 0        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design.


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design.


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 0     ; 0    ;
; Unconstrained Input Port Paths  ; 0     ; 0    ;
; Unconstrained Output Ports      ; 1     ; 1    ;
; Unconstrained Output Port Paths ; 4     ; 4    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Thu Apr 29 17:46:17 2010
Info: Command: quartus_sta druhy -c druhy
Info: qsta_default_script.tcl version: #2
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "direction[1]|combout" is a latch
    Warning: Node "direction[3]|combout" is a latch
    Warning: Node "direction[2]|combout" is a latch
Critical Warning: Synopsys Design Constraints File file not found: 'druhy.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: Deriving Clocks
    Info: create_clock -period 1.000 -name clk clk
Warning: Found combinational loop of 2 nodes
    Warning: Node "q$latch~36|datac"
    Warning: Node "q$latch~36|combout"
Warning: The following clock transfers have no clock uncertainty assignment
    Warning: From clk (Rise) to clk (Rise) (setup and hold)
Info: Analyzing Slow 1200mV 85C Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -1.061
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -1.061        -3.011 clk 
Info: Worst-case hold slack is 0.464
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.464         0.000 clk 
Info: No recovery paths to report
Info: No removal paths to report
Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.
Info: Analyzing Slow 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found combinational loop of 2 nodes
    Warning: Node "q$latch~36|datac"
    Warning: Node "q$latch~36|combout"
Warning: The following clock transfers have no clock uncertainty assignment
    Warning: From clk (Rise) to clk (Rise) (setup and hold)
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -0.871
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -0.871        -2.441 clk 
Info: Worst-case hold slack is 0.415
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.415         0.000 clk 
Info: No recovery paths to report
Info: No removal paths to report
Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.
Info: Analyzing Fast 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found combinational loop of 2 nodes
    Warning: Node "q$latch~36|datac"
    Warning: Node "q$latch~36|combout"
Warning: The following clock transfers have no clock uncertainty assignment
    Warning: From clk (Rise) to clk (Rise) (setup and hold)
Info: Worst-case setup slack is 0.127
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.127         0.000 clk 
Info: Worst-case hold slack is 0.193
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.193         0.000 clk 
Info: No recovery paths to report
Info: No removal paths to report
Critical Warning: Timing requirements not met
Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 26 warnings
    Info: Peak virtual memory: 185 megabytes
    Info: Processing ended: Thu Apr 29 17:46:20 2010
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02


