TimeQuest Timing Analyzer report for nano
Thu Apr 15 17:15:01 2010
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Clocks
  4. Slow 1200mV 85C Model Fmax Summary
  5. Slow 1200mV 85C Model Setup Summary
  6. Slow 1200mV 85C Model Hold Summary
  7. Slow 1200mV 85C Model Recovery Summary
  8. Slow 1200mV 85C Model Removal Summary
  9. Slow 1200mV 85C Model Minimum Pulse Width
 10. Propagation Delay
 11. Minimum Propagation Delay
 12. Slow 1200mV 0C Model Fmax Summary
 13. Slow 1200mV 0C Model Setup Summary
 14. Slow 1200mV 0C Model Hold Summary
 15. Slow 1200mV 0C Model Recovery Summary
 16. Slow 1200mV 0C Model Removal Summary
 17. Slow 1200mV 0C Model Minimum Pulse Width
 18. Propagation Delay
 19. Minimum Propagation Delay
 20. Fast 1200mV 0C Model Setup Summary
 21. Fast 1200mV 0C Model Hold Summary
 22. Fast 1200mV 0C Model Recovery Summary
 23. Fast 1200mV 0C Model Removal Summary
 24. Fast 1200mV 0C Model Minimum Pulse Width
 25. Propagation Delay
 26. Minimum Propagation Delay
 27. Multicorner Timing Analysis Summary
 28. Progagation Delay
 29. Minimum Progagation Delay
 30. Board Trace Model Assignments
 31. Input Transition Times
 32. Slow Corner Signal Integrity Metrics
 33. Fast Corner Signal Integrity Metrics
 34. Clock Transfers
 35. Report TCCS
 36. Report RSKM
 37. Unconstrained Paths
 38. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                    ;
+--------------------+-------------------------------------------------+
; Quartus II Version ; Version 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name      ; nano                                            ;
; Device Family      ; Cyclone III                                     ;
; Device Name        ; EP3C5E144C8                                     ;
; Timing Models      ; Final                                           ;
; Delay Model        ; Combined                                        ;
; Rise/Fall Delays   ; Enabled                                         ;
+--------------------+-------------------------------------------------+


----------
; Clocks ;
----------
No clocks to report.


--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.


---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.


--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


---------------------------------------------
; Slow 1200mV 85C Model Minimum Pulse Width ;
---------------------------------------------
Nothing to report.


+----------------------------------------------------+
; Propagation Delay                                  ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; A          ; Y1          ;    ; 5.207 ; 5.292 ;    ;
; A          ; Y2          ;    ; 5.081 ; 5.168 ;    ;
; A          ; Y3          ;    ; 5.207 ; 5.292 ;    ;
; A          ; Y4          ;    ; 8.217 ; 8.460 ;    ;
; B          ; Y1          ;    ; 4.912 ; 4.964 ;    ;
; B          ; Y2          ;    ; 4.786 ; 4.840 ;    ;
; B          ; Y3          ;    ; 4.912 ; 4.964 ;    ;
; B          ; Y4          ;    ; 7.922 ; 8.132 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------+
; Minimum Propagation Delay                          ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; A          ; Y1          ;    ; 5.111 ; 5.189 ;    ;
; A          ; Y2          ;    ; 4.991 ; 5.070 ;    ;
; A          ; Y3          ;    ; 5.111 ; 5.189 ;    ;
; A          ; Y4          ;    ; 8.105 ; 8.342 ;    ;
; B          ; Y1          ;    ; 4.850 ; 4.904 ;    ;
; B          ; Y2          ;    ; 4.730 ; 4.785 ;    ;
; B          ; Y3          ;    ; 4.850 ; 4.904 ;    ;
; B          ; Y4          ;    ; 7.844 ; 8.057 ;    ;
+------------+-------------+----+-------+-------+----+


-------------------------------------
; Slow 1200mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.


--------------------------------------
; Slow 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.


-------------------------------------
; Slow 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


--------------------------------------------
; Slow 1200mV 0C Model Minimum Pulse Width ;
--------------------------------------------
Nothing to report.


+----------------------------------------------------+
; Propagation Delay                                  ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; A          ; Y1          ;    ; 5.095 ; 5.166 ;    ;
; A          ; Y2          ;    ; 4.962 ; 5.055 ;    ;
; A          ; Y3          ;    ; 5.095 ; 5.166 ;    ;
; A          ; Y4          ;    ; 8.085 ; 8.312 ;    ;
; B          ; Y1          ;    ; 4.828 ; 4.860 ;    ;
; B          ; Y2          ;    ; 4.695 ; 4.749 ;    ;
; B          ; Y3          ;    ; 4.828 ; 4.860 ;    ;
; B          ; Y4          ;    ; 7.818 ; 8.006 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------+
; Minimum Propagation Delay                          ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; A          ; Y1          ;    ; 4.999 ; 5.070 ;    ;
; A          ; Y2          ;    ; 4.873 ; 4.964 ;    ;
; A          ; Y3          ;    ; 4.999 ; 5.070 ;    ;
; A          ; Y4          ;    ; 7.974 ; 8.202 ;    ;
; B          ; Y1          ;    ; 4.769 ; 4.804 ;    ;
; B          ; Y2          ;    ; 4.643 ; 4.698 ;    ;
; B          ; Y3          ;    ; 4.769 ; 4.804 ;    ;
; B          ; Y4          ;    ; 7.744 ; 7.936 ;    ;
+------------+-------------+----+-------+-------+----+


--------------------------------------
; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.


-------------------------------------
; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


--------------------------------------------
; Fast 1200mV 0C Model Minimum Pulse Width ;
--------------------------------------------
Nothing to report.


+----------------------------------------------------+
; Propagation Delay                                  ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; A          ; Y1          ;    ; 2.486 ; 3.139 ;    ;
; A          ; Y2          ;    ; 2.421 ; 3.077 ;    ;
; A          ; Y3          ;    ; 2.486 ; 3.139 ;    ;
; A          ; Y4          ;    ; 4.365 ; 5.262 ;    ;
; B          ; Y1          ;    ; 2.355 ; 3.005 ;    ;
; B          ; Y2          ;    ; 2.290 ; 2.943 ;    ;
; B          ; Y3          ;    ; 2.355 ; 3.005 ;    ;
; B          ; Y4          ;    ; 4.234 ; 5.128 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------+
; Minimum Propagation Delay                          ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; A          ; Y1          ;    ; 2.447 ; 3.091 ;    ;
; A          ; Y2          ;    ; 2.385 ; 3.032 ;    ;
; A          ; Y3          ;    ; 2.447 ; 3.091 ;    ;
; A          ; Y4          ;    ; 4.319 ; 5.206 ;    ;
; B          ; Y1          ;    ; 2.328 ; 2.978 ;    ;
; B          ; Y2          ;    ; 2.266 ; 2.919 ;    ;
; B          ; Y3          ;    ; 2.328 ; 2.978 ;    ;
; B          ; Y4          ;    ; 4.200 ; 5.093 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                        ;
+------------------+-------+------+----------+---------+---------------------+
; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; N/A                 ;
+------------------+-------+------+----------+---------+---------------------+


+----------------------------------------------------+
; Progagation Delay                                  ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; A          ; Y1          ;    ; 5.207 ; 5.292 ;    ;
; A          ; Y2          ;    ; 5.081 ; 5.168 ;    ;
; A          ; Y3          ;    ; 5.207 ; 5.292 ;    ;
; A          ; Y4          ;    ; 8.217 ; 8.460 ;    ;
; B          ; Y1          ;    ; 4.912 ; 4.964 ;    ;
; B          ; Y2          ;    ; 4.786 ; 4.840 ;    ;
; B          ; Y3          ;    ; 4.912 ; 4.964 ;    ;
; B          ; Y4          ;    ; 7.922 ; 8.132 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------+
; Minimum Progagation Delay                          ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; A          ; Y1          ;    ; 2.447 ; 3.091 ;    ;
; A          ; Y2          ;    ; 2.385 ; 3.032 ;    ;
; A          ; Y3          ;    ; 2.447 ; 3.091 ;    ;
; A          ; Y4          ;    ; 4.319 ; 5.206 ;    ;
; B          ; Y1          ;    ; 2.328 ; 2.978 ;    ;
; B          ; Y2          ;    ; 2.266 ; 2.919 ;    ;
; B          ; Y3          ;    ; 2.328 ; 2.978 ;    ;
; B          ; Y4          ;    ; 4.200 ; 5.093 ;    ;
+------------+-------------+----+-------+-------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Y2            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Y3            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Y4            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Y1            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; B                       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; A                       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Y2            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8e-007 V                     ; 3.09 V              ; -0.014 V            ; 0.082 V                              ; 0.136 V                              ; 1.32e-009 s                 ; 1.29e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 8e-007 V                    ; 3.09 V             ; -0.014 V           ; 0.082 V                             ; 0.136 V                             ; 1.32e-009 s                ; 1.29e-009 s                ; Yes                       ; Yes                       ;
; Y3            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8e-007 V                     ; 3.09 V              ; -0.014 V            ; 0.082 V                              ; 0.136 V                              ; 1.32e-009 s                 ; 1.29e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 8e-007 V                    ; 3.09 V             ; -0.014 V           ; 0.082 V                             ; 0.136 V                             ; 1.32e-009 s                ; 1.29e-009 s                ; Yes                       ; Yes                       ;
; Y4            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8e-007 V                     ; 3.08 V              ; 8e-007 V            ; 0.07 V                               ; 0.172 V                              ; 7.27e-009 s                 ; 7.07e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 8e-007 V                    ; 3.08 V             ; 8e-007 V           ; 0.07 V                              ; 0.172 V                             ; 7.27e-009 s                ; 7.07e-009 s                ; Yes                       ; Yes                       ;
; Y1            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8e-007 V                     ; 3.09 V              ; -0.014 V            ; 0.082 V                              ; 0.136 V                              ; 1.32e-009 s                 ; 1.29e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 8e-007 V                    ; 3.09 V             ; -0.014 V           ; 0.082 V                             ; 0.136 V                             ; 1.32e-009 s                ; 1.29e-009 s                ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.58e-007 V                  ; 3.13 V              ; -0.0981 V           ; 0.164 V                              ; 0.131 V                              ; 3.14e-010 s                 ; 3.99e-010 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 2.58e-007 V                 ; 3.13 V             ; -0.0981 V          ; 0.164 V                             ; 0.131 V                             ; 3.14e-010 s                ; 3.99e-010 s                ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.51e-007 V                  ; 2.34 V              ; -0.00718 V          ; 0.108 V                              ; 0.027 V                              ; 6.58e-010 s                 ; 8.2e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.51e-007 V                 ; 2.34 V             ; -0.00718 V         ; 0.108 V                             ; 0.027 V                             ; 6.58e-010 s                ; 8.2e-010 s                 ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Y2            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.98e-007 V                  ; 3.52 V              ; -0.0537 V           ; 0.251 V                              ; 0.255 V                              ; 8.74e-010 s                 ; 8.74e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.98e-007 V                 ; 3.52 V             ; -0.0537 V          ; 0.251 V                             ; 0.255 V                             ; 8.74e-010 s                ; 8.74e-010 s                ; No                        ; No                        ;
; Y3            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.98e-007 V                  ; 3.52 V              ; -0.0537 V           ; 0.251 V                              ; 0.255 V                              ; 8.74e-010 s                 ; 8.74e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.98e-007 V                 ; 3.52 V             ; -0.0537 V          ; 0.251 V                             ; 0.255 V                             ; 8.74e-010 s                ; 8.74e-010 s                ; No                        ; No                        ;
; Y4            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.98e-007 V                  ; 3.47 V              ; -0.00882 V          ; 0.317 V                              ; 0.303 V                              ; 4.78e-009 s                 ; 4.88e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.98e-007 V                 ; 3.47 V             ; -0.00882 V         ; 0.317 V                             ; 0.303 V                             ; 4.78e-009 s                ; 4.88e-009 s                ; No                        ; No                        ;
; Y1            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.98e-007 V                  ; 3.52 V              ; -0.0537 V           ; 0.251 V                              ; 0.255 V                              ; 8.74e-010 s                 ; 8.74e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.98e-007 V                 ; 3.52 V             ; -0.0537 V          ; 0.251 V                             ; 0.255 V                             ; 8.74e-010 s                ; 8.74e-010 s                ; No                        ; No                        ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.53e-008 V                  ; 3.65 V              ; -0.243 V            ; 0.406 V                              ; 0.304 V                              ; 1.57e-010 s                 ; 2.13e-010 s                 ; No                         ; Yes                        ; 3.46 V                      ; 6.53e-008 V                 ; 3.65 V             ; -0.243 V           ; 0.406 V                             ; 0.304 V                             ; 1.57e-010 s                ; 2.13e-010 s                ; No                        ; Yes                       ;
; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.54e-008 V                  ; 2.7 V               ; -0.0113 V           ; 0.274 V                              ; 0.034 V                              ; 3.18e-010 s                 ; 4.96e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.54e-008 V                 ; 2.7 V              ; -0.0113 V          ; 0.274 V                             ; 0.034 V                             ; 3.18e-010 s                ; 4.96e-010 s                ; No                        ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


-------------------
; Clock Transfers ;
-------------------
No clock transfers to report.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design.


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design.


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 2     ; 2    ;
; Unconstrained Input Port Paths  ; 8     ; 8    ;
; Unconstrained Output Ports      ; 4     ; 4    ;
; Unconstrained Output Port Paths ; 8     ; 8    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Thu Apr 15 17:14:58 2010
Info: Command: quartus_sta nano -c nano
Info: qsta_default_script.tcl version: #2
Critical Warning: Synopsys Design Constraints File file not found: 'nano.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning: No clocks defined in design.
Info: No clocks to report
Info: Analyzing Slow 1200mV 85C Model
Info: No fmax paths to report
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: At least one of the filters had some problems and could not be matched.
    Warning: * could not be matched with a register.
Info: No minimum pulse width or minimum period width checks to report
Info: Analyzing Slow 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning: No clocks defined in design.
Info: No fmax paths to report
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: At least one of the filters had some problems and could not be matched.
    Warning: * could not be matched with a register.
Info: No minimum pulse width or minimum period width checks to report
Info: Analyzing Fast 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning: No clocks defined in design.
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: At least one of the filters had some problems and could not be matched.
    Warning: * could not be matched with a register.
Info: No minimum pulse width or minimum period width checks to report
Warning: At least one of the filters had some problems and could not be matched.
    Warning: * could not be matched with a clock.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 12 warnings
    Info: Peak virtual memory: 184 megabytes
    Info: Processing ended: Thu Apr 15 17:15:01 2010
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02


